The active geometries of transistors may be joined together to eliminate the shallow trench isolation to reduce area and reduce cost in scaled-down technologies. For example two transistors, 16 and 18, with different transistor widths 21 and 23 as shown in FIG. 1 may be joined together as shown in FIGS. 2A and 2B. By joining the two active areas 20 and 22 together, the shallow trench isolation (STI) in dimension 28 may be eliminated significantly reducing the area of the two series transistors. Dummy gates 30 typically surround the transistor gates, 24 and 26, at a fixed pitch to improve patterning of the gates and also to control the profile of the gate during plasma etch.
In FIG. 2A two active jogs, 32 and 34, are formed in the active geometry where the wide transistor active transitions to the narrow transistor active.
In FIG. 2B one active jog, 36 is formed in the active geometry where the wide transistor active transitions to the narrow transistor active.
One problem with the transistor structure with joined active geometries is that the active area overlap of the wide transistor is no longer uniform across the width of the wide transistor. In FIG. 1, active area overlaps (e.g., 27) of the gate are of uniform width across the length of the transistor so series resistance due to the active areas is uniform. In FIG. 2B, the active area overlap 37 of the gate above the active jog 36 is significantly less than that active overlap 33 below the active jog 36. The narrow active width 37 may also result in poor silicide formation additionally increasing series resistance and degrading the transistor performance.
In scaled-down technologies, the close proximity of the jog to the gate of the wide transistor 26 has a pronounced impact on the channel width of the wide transistor due to photolithographic effects.
In FIG. 3 the active jog is placed midway between the gate of the wide width transistor 46 and the gate of the narrow width transistor 48. The active overlap 44 of the wide transistor gate 46 is about equal to the active spacing 42 to the narrow width transistor gate 48.
The percentage change in channel width of the wide transistor 46 as a function of the jog height 40 is shown by plot 60 in FIG. 5. As is shown in the graph, when the jog height exceeds about 20 nm, the percentage change in transistor width do to lithographic effects exceeds about 15%. Typically circuit simulators do not take this variation into account. Not taking this much variation into account may cause the circuit to fail.
To reduce the variation due to photolithographic effects and to reduce the difference in the active overhang of wide transistor gate above the jog and the active overhang of wide transistor gate below the jog, the jog may be placed midway between the wide and narrow transistor gates. Instead the jog may be moved closer to the narrow width transistor to increase the active overlap of wide width transistor gate as shown in FIG. 4. In FIG. 4, the active overhang 52 of wide transistor gate 56 is about double the active spacing 57 to the narrow transistor gate 58.
The percentage change (ΔW 57/W 53) in channel width 53 of the wide transistor 56 as a function of the jog height is shown by plot 62 in FIG. 5. As is shown in the graph, when the jog height exceeds about 20 nm, the change in transistor width do to lithographic effects exceeds about 11%. Typically circuit simulators do not take this variation into account. Not taking this much variation into account may cause the circuit to fail.
Scaled-down technologies often rely on strain engineering to boost the carrier mobility in the channel. Electron mobility in the channel of an NFET may be enhanced by applying tensile stress to the NFET channel and hole mobility in the channel of a PFET may be enhanced by applying compressive stress to the PFET channel.
For example, in the case of silicon substrates, p-channel field effect transistors (PFETS) are typically fabricated on substrates with a <100> crystallographic surface orientation. In <100> silicon the mobility of holes, which are the majority carriers in PFET can be increased by applying a compressive longitudinal stress to the channel. A compressive longitudinal stress is typically applied to the channel of a PFET by etching silicon from the source and drain regions and replacing it with epitaxially grown SiGe. Crystalline SiGe has a larger lattice constant than silicon and consequently causes deformation of the silicon matrix that, in turn, compresses the silicon in the channel region. Compression of the silicon lattice in the channel causes a separation of the light and heavy hole bands with a resulting enhancement of the low-field hole mobility. The increased hole mobility improves the PFET performance.
Because the lattice constant of single crystal SiGe is larger than the lattice constant of single crystal Si, the SiGe is under significant compressive stress during epitaxial crystal growth. To minimize stress, it is thermodynamically favorable to form facets 80 as is shown in FIG. 6. These facets 80 typically are formed at the SiGe 78/STI 84 (shallow trench isolation dielectric) interface. These facets reduce the amount of SiGe next to the transistor channel region 82 and therefore reduce the stress applied to the channel of the transistor that lies beneath the transistor gate 76. Thus when facets 80 are formed the performance of the PFET is degraded. In addition, faceting may result in an increase in threading dislocations and an increase in diode leakage. The SiGe may be formed next to the transistor sidewalls 74 as shown in FIG. 6 or may be formed next to the transistor gate 76 prior to formation of the transistor sidewalls 74. Forming SiGe in closer proximity to the channel region increases the compressive stress applied to the channel.
As shown in FIG. 7, one method of eliminating the SiGe/STI dielectric interface where faceting typically occurs is to form a dummy gate 92 overlying the STI dielectric/silicon interface. This prevents SiGe from coming into contact with the STI dielectric where faceting typically occurs.
Transistor structures with active jogs such as are shown in FIGS. 2A and 2B are especially problematic for PFETS with epitaxial SiGe stress enhancement and for NFETS with epitaxial SiC stress enhancement. Faceting which reduces stress enhancement decreasing transistor performance and increased threading dislocations which cause excessive diode leakage are commonly formed during epitaxial growth of SiGe or SiC next to jogs. Consequently design rules which forbid active jogs when stress enhancement is to be used are commonly used. These design rules result in increased transistor area and increased cost.